Xilinx csu. The CSU authenticates the FSBL, and optionally the PMUFW, while in internal memory. (Note: you must enable a wake-up source first otherwise the kernel will 文章浏览阅读2. The CSU comprises two main blocks as shown in the following figure. Refer chapter 11 and 12 of Zynq UltraScale+ Device Technical Reference Manual (UG1085) to understand different boot modes and features available for secure, encrypted and normal boot. Read about the LMP release v83, including support for secure boot authentication on the Xilinx Zynq® UltraScale+™ MPSoC family of products. On ZynqMP, the CSU_DMA is present inside CSU (Configuration Security Unit) module which is located within the Low-Power Subsystem (LPS) internal to the PS csu_multi_boot (CSU) Register Description Register Name csu_multi_boot Offset Address 0x0000000010 Absolute Address 0x00FFCA0010 (CSU) Width 32 Type rwNormal read/write Reset Value 0x00000000 Description Multiboot Address csu_multi_boot (CSU) Register Bit-Field Summary Field Name Bits Type Reset Value Description ssss_ Nov 20, 2025 · The Zynq UltraScale+ Device Technical Reference Manual (UG1085) provides details on CSU and PMU. XIlinx SoC drivers Zynq MPSoC SoC [*] Enable Xilinx Zynq MPSoC Power Management Driver [*] Enable Zynq MPSoC generic PM domains Firmware Drivers Zynq MPSoC Firmware Drivers -*- Enable Xilinx Zynq MPSoC firmware interface Type the following command to suspend the kernel. The sequence is as follows: BootROM searches for a valid image identification string (XLNX a This page provides information on secure boot implementation for Zynq boards using FoundriesFactory. PMU Firmware can be loaded by either FSBL or by CSU BootROM (CBR). •后配置阶段 (Post-configuration) 开始执行FSBL之后，CSU ROM代码进入后配置阶段，该阶段负责系统干预响应。 CSU硬件提供持续的硬件支持，以验证文件，通过PCAP配置PL，存储和管理安全密钥以及解密文件。 这个阶段会启动SSBL，就是Linux的bootloader，开始引导启动Linux CSU_BR_ERROR (PMU_GLOBAL) Register Description Register Name CSU_BR_ERROR Offset Address 0x0000000528 Absolute Address 0x00FFD80528 (PMU_GLOBAL) Width 32 Type mixedMixed types. (Note: you must enable a wake-up source first otherwise the kernel will Learn about building and customizing the First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC, including features, options, and common FAQs. This guide provides instructions for using the Xilinx DRM VPSS Scaler driver with CSC on Zynq UltraScale MPSoC. Secure boot in Zynq® UltraScale+™ MPSoCs is accomplished by combining the Hardware Root of Trust (HWRoT) capabilities with the option of encrypting all boot partitions. If the CSU detects partitions that are encrypted, the CSU performs decryption and loads the FSBL into the OCM. I'm looking for CSU_BR_ERR_TYPE (BIT104_CSU_BR_ERR_TYPE) into per bit. The Xilinx UltraScale MPSoC architecture, the Vivado Design Suite and additional design abstraction tools combine to break system-level processing bottlenecks through multiple technology breakthroughs. These options are available under CSU Tamper Response settings on the Advanced Configuration page. In use cases where you want two BIN files - stable and upgradable, PMU firmware can. To simplify the design process for such sophisticated devices, Xilinx offers the Vivado Design Suite, Xilinx Software Development Kit (SDK), and PetaLinux Tools for Linux. The CSU can be configured to have secure lock down, system reset, and system interrupt for some of the errors like PL single event upset (SEU) error, Temperature alarm, voltage alarm, etc. The DMA is effectively able to transfer data: Jerry Wong System Software & SoC Solutions – Product and Technical Marketing Read the CSU Register in the ATF I can successfully read the csu_multi_boot register from within the ATF, how could I pass this into U-Boot? Write an interface and get U-Boot or the kernel to call the function compiled within the ATF which does the read of the csu_multi_boot address? After boot, the CSU provides tamper response monitoring The CSU does the following Performs an authentication check and proceeds only if the authentication check passes. The HWRoT is based on the RSA-4096 Jun 16, 2023 · The CSU can be configured to have secure lock down, system reset, and system interrupt for some of the errors like PL single event upset (SEU) error, Temperature alarm, voltage alarm, etc. In this configuration stage, the BootROM (part of the CSU ROM code) interprets the boot header to configure the system and load the processing system’s (PS) first-stage boot loader (FSBL) code into the on-chip RAM (OCM I am currently trying to implement a bare-metal application for Zynq MPSoC that is supposed to reconfigure the PL. Contribute to Xilinx/embeddedsw development by creating an account on GitHub. How can I access it from U-Boot? nterrupts can be either edge triggered or level triggered. The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC (read) channel and DST (write) channel. The FreeRTOS Application works fine when I run it from JTAG (with the application's PMUFW). To work within the functionality of the MPSoC CSU ROM, the Image Selector application that is launched at power-on reset (POR) to select which boot. Node Assignments A PM Master may request and release only those PM Nodes to which they have been assigned. Secure Boot Flow In the secure boot mode, the PMU releases the reset of the configuration security unit (CSU) and enters the PMU server mode where it monitors power. Before the CSU_DMA transfer to the PCAP, the xilfpga library resets the PL and the PS_INIT_B is set to a low level. 8 Scan清除功能 归零化过程中，所有的存储元素都要移位归零，然后再验证该操作是否正确。 这是由MBIST和scan清除功能实现的。 scan清除引擎只能由PMU和CSU处理器通过直接接口进行控制，其他处理器如果要请求启动任何特定的can清除引擎都必须通过SCAN_CLR_REQ寄存 Explore the xilsecure library on Xilinx Wiki for comprehensive details on its functionality, features, and implementation guidelines for developers. This set of tools provides you with everything you need to simplify embedded system design for a device that merges an SoC with an FPGA. The Xilinx Zynq UltraScale+ is a multi-processor system on chip, that contains up to 4 ARM Cortex-A53 application processor cores, 2 ARM Cortex-R5 real-time processor cores and user-programmable logic (FGPA). Thanks. After the PMU releases the CSU from reset, the CSU checks to determine if authentication is required by the FSBL or the user application. . In I'm seeing the folowing build errors when I try to rebuild pmu firmware (either from xsct, manually or yocto). + . The QSPI has a dedicated region for maintaining persistent boot state registers and the associated boot image offsets. On the left is the secure processor block that contains a triple redundant processor for controlling boot operation. To that end, we’re removing non-inclusive language from our products and related collateral. On ZynqMP, the CSU_DMA is present inside CSU (Configuration Security Unit) module which is located within the Low-Power Subsystem (LPS) internal to the PS. Hi <p></p><p></p>When booting a Zynq Ultrascale\+ device from SD card the question arose<p></p><p></p>Once the CSU Bootrom execute and try to access the SD card to load FSBL ( assuming everything else is set up correctly ), If access failure occur ( example SD card not ready yet ) will the Boortom retry to access for several attempts or exit Where can find the detail description or documentation about the ERROR associated the BOOT. Infineon TPM, perform the measurements of the CSU ROM, FSBL, and other software partitions, and update the platform configuration registers (PCRs) with the measurements. bin image is used by passing a different offset to the CSU multi-boot register. 2. CSUDMA provides an efficient data transfer mechanism between the PSS's Memory and the CSU Stream Peripherals. However U-Boot is running at EL2 Non-Secure and cannot access the secure register directly. 2) November 2, 2022 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. On the left is the secure processor Csu_status Csu_multi_boot Csu_tamper_trig Csu_ft_status Jtag_chain_status Idcode Version Csu_rom_digest (0:11) Aes_status Pcap_status Provides information about modules and registers in Zynq UltraScale+ Devices. It shall use the CSU DMA to copy the (unencrypted) bitstream from DDR to the PCAP interface. Tamper monitoring and response. reset = XLNX_CSU_DMA_INT_R_MASK \ + }, { \ Xilinx Embedded Software (embeddedsw) Development. The following are some of the important responsibilities of the configuration security unit (CSU): Secure boot. This page provides information on power management features and implementation for Zynq UltraScale+ MPSoC in the Linux kernel. If encrypted, the CSU also performs the decryption. Zynq UltraScale+ MPSoC Software Developer Guide UG1137 (v2022. This page provides guidance on implementing cryptographic techniques in Zynq UltraScale MPSoC for enhanced security and data protection. XSYSMONPSU_CSU_BASEADDR is the CSU's base address (0xFFCA0000) and PCAP_STATUS_OFFSET is 0x00003010. The Configuration and Security Unit (CSU) processor uses the code in the BootROM . Then checks the image for any encrypted partitions. This additional handshake step is required in boot scenarios where FSBL is started by CSU. Expand Post PL programming can be done in the FSBL, u-boot and Linux. Use Secure Boot Features to Protect Your Design The secure boot functionality in Xilinx™ devices allows you to support the confidentiality, integrity, and authentication of partitions. The Xilinx® Zynq®-7000 All Pro-grammable SoC supports confi uration of the interrupt either way, a WHY USE AN INTERRUPT- DRIVEN APPROACH? sors and the like) that will at times require process-ing. I am using the ZCU102 Evaluation Kit and Vitis Unified IDE v2023. Zynq UltraScale+ devices continue this trend by including a physical unclonable function (PUF), user-accessible hardened cryptographic blocks, asymmetric authentication, side channel attack protection, and other Xilinx Embedded Software (embeddedsw) Development. Secure key storage and management. Single thread (AXI-ID) operation for both read and write channels CSU_DMA operates synchronously in the “csu_main_clk” or PMC clock domain Target CSU_DMA frequency of 400MHz max DST DMA will only issue a write AXI command if the corresponding write data is available in the write data FIFO – Store and Forward. Inputs from these devices are generally asynchronous to the process or task currently Zynq UltraScale＋ MPSoC Power Management - Firmware Examples Zynq UltraScale+ MPSoC Power Management - Firmware Examples Table of Contents Node Assignments DDR and PLL Nodes Related Links This page provides tips and examples of PMU firmware solutions for the Zynq UltraScale+ MPSoC. Explore the Zynq UltraScale+ MPSoC on Xilinx Wiki, a comprehensive resource for information, guides, and updates on this advanced multiprocessor system-on-chip. The hardware in use is zu11eg. In this configuration stage, the BootROM (part of the CSU ROM code) interprets the boot header to configure the system and load the processing system’s (PS) first-stage boot loader (FSBL) code into the on-chip RAM (OCM Some Zynq MP registers such as CSU/PMU are secured as listed in Table 16-10 of (UG1085). There are three interrupts from CSU (PS) to PL as CSU WDT Interrupt, CSU DMA Interrupt, and CSU interrupt. In u-boot and Linux, an IPI request is sent to the PMU, and the PMUFW will use the xilfpga library to copy the bitstream to the PCAP with CSU_DMA. For specific information on CSU, see "Configuration Security Unit" in the Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137). In a Zynq UltraScale+ RFSoC device there is a BootROM for initial bring up of the device. Loading PMU firmware using FSBL has the following benefits: Possible quick boot time, when PMU firmware is loaded after bitstream. 2. In this configuration stage, the BootROM (part of the CSU ROM code) interprets the boot header to configure the system and load the processing system’s (PS) first-stage boot loader (FSBL) code into the on-chip RAM (OCM On ZynqMP, the CSU_DMA is present inside CSU (Configuration Security Unit) module which is located within the Low-Power Subsystem (LPS) internal to the PS. One external tamper interrupt is mapped to CSU through MIO. PFW must wait for CSU to trigger FSBL start otherwise there may be race condition where PFW is trying to restore state of processor as part of resume from Power Off Suspend sequence while CSU is trying to run FSBL on that same processor. Cryptographic hardware acceleration. On Versal and Versal Gen 2 it is known as PMCDMA and present in PMC (used for Platform Management). The CSU interrupt status register holds the interrupt bits PMU firmware can be loaded by either FSBL or CSU BootROM (CBR). It also contains an associated ROM, a small private RAM, and the necessary control/status registers required to support all secure operations. To implement this feature, I had a look at the FSBL source code, since it performs reconfiguration during the boot Summarizes the software-centric information required for designing with AMD Zynq™ UltraScale+™ MPSoCs. Both these flows are supported by Xilinx. The sequence is as follows: BootROM searches for a valid image identification string (XLNX a Xilinx has been at the forefront of providing FPGA and system-on-a-chip (SoC) AT solutions to its customers for many generations. mb-gcc -mlittle-endian -mxl-barrel-shift -mxl-pattern-c IDCODE (CSU) Register Description Register Name IDCODE Offset Address 0x0000000040 Absolute Address 0x00FFCA0040 (CSU) Width 32 Type roRead-only Reset Value 0x00000000 Description Device IDCODE IDCODE (CSU) Register Bit-Field Summary Field Name Bits Type Reset Value Description IDCODE 31:0 roRead-only 0 Reads the same In a Zynq UltraScale+ MPSoC device there is a BootROM for initial bring up of the device. PMU Firmware loading by CBR will be needed in the cases where the customer board has an onboard regulator that needs to be programmed to bring up the boot processor's power rail. The CSU Interrupt is used to indicate that something in the CSU logic has caused an interrupt. In the Zynq® UltraScale+™ MPSoC, the CSU bootROM supports MultiBoot and fallback boot image search where the configuration security unit CSU ROM or bootROM searches through the boot device looking for a valid image to load. Dec 3, 2025 · The CSU comprises of two main blocks as shown in the following figure. 7k次，点赞5次，收藏28次。本文介绍了XilinxMPSoc的启动流程，包括PMU处理单元的电源管理和初始化，CSU的安全与配置功能。启动分为预配置、配置和后配置三个阶段，其中FSBL在配置阶段被加载到OCM中，并在后配置阶段初始化系统，准备引导Linux或RPU应用程序。 In the AMD Zynq™ UltraScale+™ MPSoC, the CSU bootROM supports MultiBoot and fallback boot image search where the configuration security unit CSU ROM or bootROM searches through the boot device looking for a valid image to load. Provides information on CSUDMA Standalone driver for Xilinx devices, including installation, configuration, and usage details. Introduction This page gives an overview of CSUDMA driver which is available as part of the Xilinx Vivado and Vitis distribution. Or, a table table as per binary or Hex values basis. In a Zynq UltraScale+ MPSoC device there is a BootROM for initial bring up of the device. Xilinx Embedded Software (embeddedsw) Development. In the AMD Zynq™ UltraScale+™ MPSoC, the CSU bootROM supports MultiBoot and fallback boot image search where the configuration security unit CSU ROM or bootROM searches through the boot device looking for a valid image to load. For Known Issues related to the FSBL and CSU Boot Rom, Please check (Xilinx Answer 65467) In order to determine this, program an image with FSBL debug prints enabled. jtpusl, mnns, gyf2m, 95ii9o, flnhw, 0up9, vms1, kxv9, ynb2, y5zow,